Digital Techniques (DTE)

Multiple Choice Questions (MCQs)

1   The following Boolean function equivalent to. F (A, B, C, D) = π (1, 3, 5, 7, 13, 15)
    (A)   a) BD’+ACD’
    (B)   b) BD’+ACD’+ABC’D
    (C)   c) (B+D’) (A+C+D’)
    (D)   d) (A+D’) (B’+D’)
[showhide type=”button7c1″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
2   The binary number 100111 is equivalent to decimal number ………….
    (A)   39
    (B)   37
    (C)   35
    (D)   21
[showhide type=”button7c2″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
3   The universal gate is ………………
    (A)   Ex NOR gate
    (B)   OR gate
    (C)   AND gate
    (D)   NOR gate
[showhide type=”button7c3″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
4   The inverter is following Logic Gate
    (A)   NAND gate
    (B)   OR gate
    (C)   AND gate
    (D)   NOT gate
[showhide type=”button7c4″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
5   2’s complement of binary number 0001 is ……….
    (A)   1011
    (B)   1111
    (C)   1101
    (D)   1110
[showhide type=”button7c5″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
6   Decimal number 1010 is equal to octal number ……………
    (A)   1762
    (B)   1010
    (C)   1011
    (D)   1760
[showhide type=”button7c6″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
7   In 1’s complement representation the number 11100101 represents the decimal number
    (A)   37
    (B)   -31
    (C)   27
    (D)   -26
[showhide type=”button7c7″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
8   For the gate in the given figure the output will be ……….
    (A)   0
    (B)   1
    (C)   A
    (D)   Ā
[showhide type=”button7c8″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
9   The number of digits in Duodecimal system is ………
    (A)   16
    (B)   15
    (C)   10
    (D)   12
[showhide type=”button7c9″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
10   Decimal 59 in hexadecimal and BCD number system is respectively……. and …….
    (A)   B3 and 01011001
    (B)   3B and 01010001
    (C)   3B and 01011001
    (D)   B3 and 01000100
[showhide type=”button7c10″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
11   Decimal number 1010 is equal to gray code ……………
    (A)   1010
    (B)   1110
    (C)   1111
    (D)   1011
[showhide type=”button7c11″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
12   The NAND gate is AND gate followed by …………………
    (A)   NOT gate
    (B)   OR gate
    (C)   AND gate
    (D)   None of the above
[showhide type=”button7c12″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
13   Digital circuit can be made by the repeated use of ………………
    (A)   OR gates
    (B)   NOT gates
    (C)   NAND gates
    (D)   None of the above
[showhide type=”button7c13″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
14   An OR gate has 7 inputs. Two inputs are high and the others are low. The output is …….
    (A)   Low
    (B)   High
    (C)   alternately high and low
    (D)   may be high or low depending on relative magnitude of inputs
[showhide type=”button7c14″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
15   Logical Expression for Ex NOR gate is
    (A)   AB+A’B’
    (B)   AB+A’B
    (C)   A’B+AB’
    (D)   AB’+AB’
[showhide type=”button7c15″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
16   The full form of CMOS is ____________
    (A)   Capacitive metal oxide semiconductor
    (B)   Capacitive metallic oxide semiconductor
    (C)   Complementary metal oxide semiconductor
    (D)   Complemented metal oxide semiconductor
[showhide type=”button7c16″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
17   Which of the following logic expressions represents the logic diagram shown?

    (A)   X=AB’+A’B
    (B)   X=(AB)’+AB
    (C)   X=(AB)’+A’B’
    (D)   X=A’B’+AB
[showhide type=”button7c17″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
18   Total number of inputs in a Full adder is __________
    (A)   2
    (B)   3
    (C)   4
    (D)   1
[showhide type=”button7c18″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
19   The full subtractor can be implemented using ___________
    (A)   Two XOR and an OR gates
    (B)   Two half subtractors and an OR gate
    (C)   Two multiplexers and an AND gate
    (D)   Two comparators and an AND gate
[showhide type=”button7c19″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
20   Which statement below best describes a Karnaugh map?
    (A)   It is simply a rearranged truth table
    (B)   The Karnaugh map eliminates the need for using NAND and NOR gates
    (C)   Variable complements can be eliminated by using Karnaugh maps
    (D)   A Karnaugh map can be used to replace Boolean rules
[showhide type=”button7c20″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
21   Which of the following expressions is in the sum-of-products form?
    (A)   (A + B) (C + D)
    (B)   (A * B) (C * D)
    (C)   A* B *(CD)
    (D)   A * B + C * D
[showhide type=”button7c21″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
22   A code converter is a logic circuit that _____________
    (A)   Inverts the given input
    (B)   Converts into decimal number
    (C)   Converts data of one type into another type
    (D)   Converts to octal
[showhide type=”button7c22″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
23   The logical equation of code of digital lock is A’BCD’…. then following two input (maximum) basic gates are required to implement above code
    (A)   two OR gate and one NOT gate
    (B)   two AND gate and two NOT gates
    (C)   three AND gate and two NOT gates
    (D)   four AND gate and two NOT gates
[showhide type=”button7c23″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
24   Which of the following is TRUE about K Map?
    (A)   only SOP functions can be obtained
    (B)   only POS functions can be obtained
    (C)   only minterm functions can be obtained
    (D)   None of the Above
[showhide type=”button7c24″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
25   Which of the following is not a basic Boolean Law?
    (A)   Associative Law
    (B)   Distributive Law
    (C)   Canonical Law
    (D)   Commutative Law
[showhide type=”button7c25″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
26   Two stable states of latches are ___________
    (A)   Astable & Monostable
    (B)   Low input & high output
    (C)   High output & low output
    (D)   Low output & high input
[showhide type=”button7c26″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
27   The SR latch consists of ___________
    (A)   1 input
    (B)   2 inputs
    (C)   3 inputs
    (D)   4 inputs
[showhide type=”button7c27″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
28   When a high is applied to the Set line of an SR latch, then ___________
    (A)   Q output goes high
    (B)   Q’ output goes high
    (C)   Q output goes low
    (D)   Both Q and Q’ go high
[showhide type=”button7c28″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
29   If A = A1A0 and B = B1B0 are two-bit input binary numbers, output C=C3C2C1C0 implements

    (A)   a two-bit-by-two-bit division
    (B)   a two-bit-by-two-bit multiplier
    (C)   a two-bit adder
    (D)   a two-bit subtractor
[showhide type=”button7c29″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
30   The flip-flop is only activated by _____________
    (A)   Positive edge trigger
    (B)   Negative edge trigger
    (C)   Either positive or Negative edge trigger
    (D)   Sinusoidal trigger
[showhide type=”button7c30″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
31   What does the direct line on the clock input of a J-K flip-flop mean?
    (A)   Level enabled
    (B)   Positive edge triggered
    (C)   negative edge triggered
    (D)   Level triggered
[showhide type=”button8c1″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
32   Modulus in in digital electronics refers to ____________
    (A)   A method used to fabricate decade counter units
    (B)   The modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
    (C)   An input on a counter that is used to set the counter state, such as UP/DOWN
    (D)   The maximum number of states in a counter sequence
[showhide type=”button8c2″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
33   The minimum number of flip-flops that can be used to construct a modulus-5 counter is ____________
    (A)   3
    (B)   8
    (C)   5
    (D)   10
[showhide type=”button8c3″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
34   The register (in Digital Electronics) is a type of ___________
    (A)   Sequential circuit
    (B)   Combinational circuit
    (C)   CPU
    (D)   Latches
[showhide type=”button8c4″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
35   A shift register is defined as ___________
    (A)   The register capable of shifting information to another register
    (B)   The register capable of shifting information either to the right or to the left
    (C)   The register capable of shifting information to the right only
    (D)   The register capable of shifting information to the left only
[showhide type=”button8c5″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
36   Find out the resolution of 8-bit DAC/ADC?
    (A)   562
    (B)   625
    (C)   256
    (D)   265
[showhide type=”button8c6″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
37   A flip-flop can be designed using
    (A)   NAND gates
    (B)   NOR gates
    (C)   basic gates such as AND, OR and NOT
    (D)   any of the above
[showhide type=”button8c7″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
38   The following circuit implements

    (A)   D flip-flop with enable input T
    (B)   J-K flip-flop
    (C)   T flip-flop
    (D)   D latch
[showhide type=”button8c8″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
39   The output Qn of a J-K (or S-R) flip-flop is 0. Its output does not change when a clock pulse is applied. The inputs Jn and Kn (or Sn and Rn) are respectively.
    (A)   X and 0
    (B)   0 and 0
    (C)   0 and X
    (D)   1 and 1
[showhide type=”button8c9″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
40   The J-K flip-flop shown below is initially cleared and then clocked for 5 pulses, the sequence at the Q output will be

    (A)   0 1 0 0 0 0
    (B)   0 1 1 0 0 1
    (C)   0 1 0 0 1 0
    (D)   0 1 0 1 0 1
[showhide type=”button8c10″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
41   Identify the circuit shown in the figure.

    (A)   Positive edge triggered D Flip Flop where X is input, Y is clock, Q is output
    (B)   Negative edge triggered D Flip Flop where X is input, Y is clock, Q is output
    (C)   Positive edge triggered D Flip Flop where Y is input, X is clock, Q is output
    (D)   Negative edge triggered D Flip Flop where Y is input, X is clock, Q is output
[showhide type=”button8c11″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]
42   Consider the 1:4 demultiplexer circuit shown below. What would be the output bits for input condition S0 = 1, S1 = 1 and Din = 1?

    (A)   Y0 = 0, Y1 = 1, Y2= 1, Y3 = 1
    (B)   Y0 = 0, Y1 = 0, Y2= 0, Y3 = 1
    (C)   Y0 = 0, Y1 = 0, Y2= 1, Y3 = 0
    (D)   Y0 = 0, Y1 = 0, Y2= 1, Y3 = 1
[showhide type=”button8c12″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
43   An SR-latch is created using only two NOR gates with S and R inputs feeding one NOR gate each. If both S and R inputs are set to one, the outputs will be
    (A)   Q and Q’ both 1
    (B)   No change in circuit output
    (C)   Q and Q’ both 0
    (D)   Q and Q’ complementary to each other
[showhide type=”button8c13″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
44   A positive edge triggered D flip flop is connected as shown in the figure below. What would be the Q output in relation to the clock? Assume Q is initially 0.

    (A)   Timing Diagram A
    (B)   Timing Diagram B
    (C)   Timing Diagram C
    (D)   Timing Diagram D
[showhide type=”button8c14″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: D [/showhide]
45   How many flip-flops will be complemented in a 10‐bit binary ripple up counter to reach the next count after the count 1001100111. (Assume all flip-flops are positively triggered)
    (A)   3
    (B)   2
    (C)   4
    (D)   1
[showhide type=”button8c15″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
46   A binary ripple counter uses flip‐flops that trigger on the positive‐edge of the clock. What will be the count if the normal outputs of the flip‐flops are connected to the clock input of the next stage.
    (A)   A count up counter
    (B)   A count down counter
    (C)   A BCD counter
    (D)   A Gray code sequence generator
[showhide type=”button8c16″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
47   A 4-bit shift register circuit configured for right-shift operation (Din->A, A->B, B->C, C->D), is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 0100 is

    (A)   3
    (B)   7
    (C)   4
    (D)   5
[showhide type=”button8c17″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: C [/showhide]
48   The race around condition occurs in a J-K flip-flop when
    (A)   both inputs are 0
    (B)   both inputs are 1
    (C)   the inputs are complementary
    (D)   J=0 and K = 1
[showhide type=”button8c18″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
49   In general, a sequential logic circuits consists of
    (A)   only flip-flops
    (B)   flip-flops and combinational logic circuits
    (C)   only basic gates
    (D)   only combinational logic circuits
[showhide type=”button8c19″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: B [/showhide]
50   What would be the number of flip flops required to design mod-10 ring counter and mod-10 Johnson counter respectively?
    (A)   10 and 5
    (B)   10 and 10
    (C)   5 and 5
    (D)   5 and 10
[showhide type=”button8c20″ more_text=”Show Answer” less_text=”Hide Answer”] Answer: Option: A [/showhide]

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